1. Field of the Invention
The present invention relates to the field of semiconductor memories and, more particularly, to the formation of high density memory modules.
2. State of the Art
In recent history, computer memory storage devices have quadrupled in memory capacity about every three years. In order to remain competitive, semiconductor industry leaders continually strive to shrink circuit feature sizes and design more efficient memory hierarchies. Developmental costs for new chip design and fabrication processes are high, and require an equally expensive investment in new manufacturing equipment. On the other hand, consumers and other industries are striving for alternative low-cost and instantaneous solutions. One such solution is “memory stacking.”
Identical memory devices have corresponding address, power supply, and data lines that may be paralleled. As a result, like memory devices may be physically stacked upon one another with the bottom device mounted on a printed circuit board or other second level package. Stacked devices are denoted by rank, with the bottom device designated as a “rank one” device. The top device of a two-deep stacking arrangement is designated as a “rank two” device. Multiple ranks may exist with each rank relating to the number of devices stacked underneath the ranked device. Multiple devices may exist for each rank as well.
The pins of each device or rank are connected to each other via simple soldering or often via a special connective casing. Pins receiving signals that cannot be paralleled are not connected together, and must instead have separate pin locations. Generally, the “chip select” (“CS”) pin, which, when active, selects the memory device rank for reading and writing operations, is not paralleled with other device CS pins. Because not all memory devices in a memory stack need to be activated at the same time, the CS pins have traditionally not shared signals with other CS pins.
One method of achieving separate control of each device in a stacked memory module is to extend a separate CS trace from the memory controller to each of the stacked devices. For example, FIG. 1 depicts a stacked memory module 1 comprising two stacked conventional memory devices or ranks 12. A memory controller 10 may activate each of the memory devices or ranks 12 by passing an appropriate signal along a trace carrying a first chip select signal 14 or a second chip select signal 16. Thus, in general, a stacked memory module with “n” stacked devices has “n” CS traces connecting it to the memory controller, where “n” is an integer. Although simple in concept, the limitations are apparent. Greater numbers of stacked devices will require greater numbers of CS traces. Because circuit board space is limited, this solution quickly becomes impracticable as the number of stacked devices increases.
One solution, disclosed in U.S. Pat. No. 4,884,237 which retains the original single memory device footprint, is the utilization of “no-connection” pins (“NC”). In the disclosed method, dynamic random access memory (“DRAM”) device NC pins were conductively connected to the device CS pin. Thus, wherein the lower DRAM device may receive a CS signal sent directly to the device's CS pin, the upper device may instead receive a CS signal through one of its NC pins that has been shorted to the device's CS pin. The effect is the same as in the first method: both devices receive a traditional CS signal. Similarly, the number of CS signal lines extending from the memory controller must equal the number of stacked devices. However, the advantage of the second method is that no additional pin locations are necessary, hence preserving the original memory device footprint.
As memory devices have grown more complex, however, and as the demand to stack greater numbers of memory devices has increased, the above-described methods have proven inadequate. Circuit board space is even more limited, and memory devices have only limited NC pins that may be shorted to CS pins. Memory devices, such as DRAM devices, are typically mounted on standardized dual inline memory modules (“DIMMs”) that have a set, standardized pin and trace layout. Each DIMM typically includes, for example, 18 DRAM devices, address, data, and power traces, one CS trace and one NC trace. Clearly, the one CS trace can act to select the 18 DRAM devices on the DIMM, and the NC trace may be used to send a CS signal to a second rank of 18 stacked DRAM devices (assuming the NC pins have been shorted to the CS pins on the second rank of DRAM devices), but further control of higher stacked DRAM devices is not available through the disclosed methods.
Accordingly, there is a clear need in the art for improved memory stacking and methods, particularly in the chip selection of higher density memory modules.